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up1666q 1 up1666q-ds-f0000, june 2017 www.upi-semi.com 2-phase synchronous-rectified buck controller for mobile gpu power ?? ?? ? support nvidia open vreg type-2+ pwmvid technology ?? ?? ? wide input voltage range 2.5v ~ 20v ?? ?? ? robust constant on-time control ?? ?? ? 2/1 phase operation ?? ?? ? two integrated mosfet drivers with shoot- through protection and internal bootstrap schottky diode ?? ?? ? selectable soft-start ?? ?? ? multi-function pin (fs/oc) for linear ocpthreshold setting and switching frequency selection ?? ?? ? external compensation ?? ?? ? dynamic output voltage adjustment ?? ?? ? power good indication ?? ?? ? over voltage protection ?? ?? ? under voltage protection ?? ?? ? over temperature protection ?? ?? ? rohs compliant and halogen free rebmunredr oe gakca pg nikram pot fkqq6661p ul 02-3x3nfq wq 6661pu general description applications features ordering information pin configuration the up1666q is a 2/1-phase synchronous-rectified buck controller specifically designed to work with 2.5v ~ 20v input voltage and deliver high quality output voltage for high performance graphic processor power. the up1666q adopts proprietary rcot tm technology, providing flexible selection of output lc filter and excellent transient response to load and line change. the up1666q supports nvidia open voltage regulator 2+ with pwmvid feature. the pwmvid input is buffered and filtered to generate accurate reference voltage, and the output voltage is precisely regulated to the reference input. the up1666q uses mosfet r ds(on) current sensing for channel current balance. the up1666q also implements a multi-function pin (fs/oc) for switching frequency selection and ocp threshold setting. other features include power saving control input, and power good output. this part is available in wqfn3x3- 20l package. note: (1) please check the sample/production availability with upi representatives. (2) upi products are compatible with the current ipc/jedec j-std-020 requirements. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suit- able for use in snpb or pb-free soldering processes. ?? ?? ? middle-high end gpu core power ?? ?? ? high end desktop pc memory core power ?? ?? ? low output voltage, high power density dc-dc converters ?? ?? ? voltage regulator modules phase1 4 3 2 1 ugate2fb comp psi refadj boot1 lgate1 phase2 gnd 9 8 7 6 17 18 19 20 14 13 12 15 boot2 refin en vref pgood pvcc fbrtn 5 vid 10 fs/oc ugate1 11 lgate2 16
up1666q 2 up1666q-ds-f0000, june 2017 www.upi-semi.com typical application circuit 1-phase mode fb comp phase1 en boot1 ugate1 lgate1 lgate2 ugate2 boot2 phase2 psi pvcc v in = 2.5v~20v gnd v out fbrtn pgood 1.8v vid 5v fs/oc vref refadj refin vref v ss_sns v cc_sns v ss_sns 1.8v 1.8v *note 2: unused pins can be left open. *note 3: refer to table3 for lgate2 strap setting. *note 1: refer to table2 for psi pin input voltage setting of 1-phase operation optional optional
up1666q 3 up1666q-ds-f0000, june 2017 www.upi-semi.com typical application circuit 2-phase mode fb comp phase1 en boot1 ugate1 lgate1 lgate2 ugate2 boot2 phase2 psi pvcc v in = 2.5v~20v gnd v out fbrtn pgood 1.8v vid 5v fs/oc vref refadj refin vref v ss_sns v cc_sns v ss_sns 1.8v 1.8v optional optional *note 4: refer to table2 for psi pin input voltage setting of 2-phase operation *note 5: refer to table3 for lgate2 strap setting.
up1666q 4 up1666q-ds-f0000, june 2017 www.upi-semi.com typical application circuit application for output above 2v fb comp phase1 en boot1 ugate1 lgate1 lgate2 ugate2 boot2 phase2 pvcc v in = 2.5v~20v gnd v out fbrtn pgood 1.8v vid 5v fs/oc vref refadj refin vref v ss_sns v cc_sns 1.8v psi 1.8v r3 r4 *note 6: unused pin can be left open. *note 8 *note 8: lgate1 resistor strap should be 30k. optional *note 9: refer to table3 for lgate2 strap setting. *note 7: refer to table2 for operation mode setting.
up1666q 5 up1666q-ds-f0000, june 2017 www.upi-semi.com functional pin description .on ni pe ma nn oitcnufnip 11 toob .1esahproftoob partstooba mrofot1esahpotnipsihtmorfroticapacatcennoc .1esahpehtforevirdetagreppuroftiucric 21 etagu .1esahprofrevirdetagreppu . tefsomreppu1esahpfoetagehtotnipsihttcennoc 3n e .elbane .elbanepihc 4i sp .tupnignivasrewop .upg morflangislortnocgnivasrewop seviecerniptupnina 5d iv .div .niptupnidivm w p 6j dafer .tnemtsujdaecnerefer otrotargetnicrnahtiwnipsihttcennoc.niptuptuodivm w p .egatlovniferetareneg 7n ifer .tupniecnerefer rorotsiserahguorhtegatlovecnereferlanretxenaotnipsi httcennoc .tiucricjdaferehtfotuptuoehtottcennoc 8f erv .egatlovecnerefer gnilpuocedfu1tsaeltanatcennoc.niptuptuoegatlovodlv2 .dng dnanipsihtneewtebroticapac 9c o/sf .gnittespco dnaycneuqerfgnihctiws ferv morfredividegatlovevitsiseratcennoc .ycneuqerfgnihctiwsdnadlohserhtpcotesotdng ot 0 1n trbf .tiucricecnereferehtrofnruter tuptuoerehwtniopdnuorgehtotnipsihttcennoc .detalugerebotsiegatlov 1 1b f .nipkcabdeef .reifilpmarorreehtfotupnignitrevniehtsinipsiht 2 1p moc .tuptuo noitasnepmoc .reifilpmarorreehtfotuptuoehtsinipsiht 3 1d oogp .noitacidnidoogrewop .erutcurtsniard-nep oh tiwecruosegatlovaotnipsihttcennoc .rotsiserpu-llupa 4 12 etagu .2esahprofrevirdetagreppu tefsomreppu2esahpfoetagehtotnipsihttcennoc 5 12 toob .2esahproftoob partstooba mrofot2esahpotnipsihtmorfroticapacatcennoc .2esahpehtforevirdetagreppuroftiucric 6 12 esahp .2esahprofnipesahp .2esahprofrevirdetagreppufohtapnruterehtsinipsiht etagreppuroftiucricpartstooba mrofot2toobotnipsihtmorfroticapacatcennoc .2esahpehtforevird 7 12 etagl .2esahprofrevirdetagrewol tefsomrewol2esahpfoetagehtotnipsihttcennoc 8 1c cvp .ciehtroftupniylppus ylppusv5aotnipsihttcennoc.ciehtfoylppusrewopegatlov .roticapaccimarecfu1atsaeltagnisuelpuoceddna 9 11 etagl .1esahprofrevirdetagrewol . tefsomrewol1esahpfoetagehtotnipsihttcennoc 0 21 esahp .1esahprofnipesahp .1esahprofrevirdetagreppufohtapnruterehtsinipsiht etagreppuroftiucricpartstooba mrofot1toobotnipsihtmorfroticapacatcennoc .1esahpehtforevird dapdesopxe .dnuorg noitcennocecnadepmitsewolehthguorhtenalp/dnalsidnuo rgotnipsihteit .elbaliava
up1666q 6 up1666q-ds-f0000, june 2017 www.upi-semi.com functional block diagram pvcc por gate control logic boot1 ugate 1 phase 1 lgate 1 boot2 ugate 2 phase 2 lgate 2 refin fb comp ramp generation phase selection on-time generation gate control logic current balance ovp uvp ovp uvp vref vid linear regulator h/l detector pvcc refadj fbrtn v ss fs/oc over current protection ocp a/d converter por +delay s1s2 vref v phase1 v phase2 f sw psi soft start & power ok en pgoo d otp
up1666q 7 up1666q-ds-f0000, june 2017 www.upi-semi.com functional description supply input and power on reset the up1666q receives supply input from pvcc and en pin to provide current to gate drivers and internal control circuit. the up1666q continuously monitors pvcc and en voltages to ensure all power voltages are ready for normal operation. the pvcc por level is typically 4.1v. the en high level is typically 1v. the up1666q integrates floating mosfet gate driver that are powered from the pvcc pin. a bootstrap schottky diode is embedded to facilitate pcb design and reduce the total bom cost. no external schottky diode is required in real applications. an external schottky diode with lower voltage drop can improve the power conversion efficiency. pvcc en 4.1v po r 1v figure 1. circuit of power ready detection voltage control loop and pwmvid function figure 2 illustrates the voltage control loop of the up1666q. fb and refin are negative and positive inputs of the error amplifier respectively. the error amplifier modulates the comp voltage v comp of buck converter to force fb voltage v fb follows v refin . comp refadj refin vref vid 2v r1 r3 r2 pwmvid fbrtn v ss_sns c fb r4 v stdby r stdby r5 ea figure 2. voltage control loop the pwmvid signal from gpu is applied to the vid pin, which is the input pin of the internal buffer. this buffer plays the role of level shifting, and the output of this buffer is injected into the external rc integrator to generate refin voltage, which can be calculated as: = refin v () () + + + + + + + + + 5 4 3 5 4 5 4 3 2 1 5 4 3 2 r r r r r r r r // r r r r r // r d v vref () () 5 4 3 5 4 5 4 3 1 2 5 4 3 1 r r r r r r r r // r r r r r // r v vref + + + + + + + + where v refin is the dc voltage of refin, v vref is the voltage of vref (typically 2v), and d is the duty cycle of pwmvid input. the vref pin is an internal ldo, therefore an output decoupling capacitor is required. recommend connecting at least a 1uf capacitor from vref pin to local gnd. boot voltage and standby mode the new generation pwmvid structure includes two operation modes other than normal operation: boot mode and standby mode. during boot mode, the gpu stops sending pwmvid signal and the input of the pwmvid buffer is floating. the refadj pin enters high impedance state after the vid pin enters tri-state region, and the refin voltage can then be calculated as: 5 4 3 2 5 4 r r r r r r v v vref boot , refin + + + + = during standby mode, other than gpu stopping the pwmvid transaction, an external system standby signal additionally controls the entry of standby mode. an additional external switch should be connected in parallel with the original pwmvid resistors as shown in figure 3 to generate the standby mode voltage: = stdby refin v , () () 5 4 3 5 4 5 4 3 2 5 4 3 r r r r r r // r r r r r // r r r v stdby stdby vref + + + + + + + +
up1666q 8 up1666q-ds-f0000, june 2017 www.upi-semi.com functional description refadj refin vref vid 2v r1 r3 r2 pwmvid fbrtn v ss_sns c r4 v stdby r stdby r5 figure 3. standby mode configuration operation frequency selection and ocp setting fs/oc vref r1 r2 ocp level s 3 s 1 a/d converter s 2 operation frequency 2v i source figure 4. fs/oc pin for operation frequency selection and ocp threshold setting figure 4 shows the multi-function fs/oc pin for operation frequency selection and ocp threshold setting. after pvcc por, s1, and s2 switches turn on. internal current source i source flows out to fs/oc pin to generate a voltage v fs1 . then, s2 switch turns off, the fs/oc pin voltage v fs2 is determined by the external voltage divider. controller samples/holds the v fs1 and v fs2 to calculate the ? v fs and determine the controller operation frequency according to the following table. table 1. controller operation frequency table level ?? ? ?? v sf f ws 1v m0 6z hk002 2v m02 1z hk003 3v m08 1z hk004 4v m04 2z hk005 5v m00 3z hk006 6v m06 3z hk008 after the operation frequency is determined, the up1666q turns off s1 and s2 switches and turns on s3 switch for ocp setting. when s3 is turned on, the fs/oc pin voltage is determined by the external voltage divider, and the fs/ oc pin voltage is connect to the internal ocp circuit for ocp level v oc setting. v oc is the per-phase gnd-phase voltage when the power stage low-side mosfets are turned on. when per-phase i sd,lmos *r ds(on),lmos exceeds v oc , up1666q will limit the phase current. since the oc mechanism detects per- phase current for inductor valley current limiting, the per- phase limited current can be calculated as: ) pk pk (l ) on ( ds oc phase per , max i r v i ? + = 2 1 and the total limited current can be calculated as: ? ? ? ? ? ? ? ? ? + = ) pk pk (l ) on ( ds oc total , max i r v n i 2 1 where n is the operating phase number, r ds(on) is the on- resistance of equivalent per-phase power stage low side mosfet. if any phase current exceeds i max,per-phase , the current limit protection is triggered, that phase current will be limited. up1666qs operation frequency and oc level setting is related to resistance of r1 and r2. therefore, the proper resistance of r1 and r2 is needed. the following is the equation to calculate the value of r1 and r2. oc fs v v. v ua v r + = 2 6 0 2 4 1 1 1 2 41 2 2 r v v. v r oc ? ? ? ? ? ? =
up1666q 9 up1666q-ds-f0000, june 2017 www.upi-semi.com functional description where v fs is the recommended ? v fs for operating frequency select and the v oc is the oc level for each phase. take 300khz(v fs =120mv) operation frequency and 100mv per-phase oc level as an example. the resistance of r1 and r2 should be: ? = + = k mv v. v ua mv r 75 100 2 60 2 4 120 1 ? = ? ? ? ? ? ? ? = k k mv v. v r 50 75 1 100 2 41 2 2 operation modethe up1666q provides power saving features for platform designers to program platform specific power saving configuration. there are four operation modes: full-phase ccm, full-phase dcm, single-phase ccm, and single- phase dcm. the up1666q switches between these four operation modes according to the input voltage level of the psi pin. table 2 shows recommended psi setting voltage level of four operation modes. in single-phase operation, the up1666q auto-selects phase 1 to be the operating phase. dcm operation mode is activated by two conditions: 1. psi voltage stays at single-phase dcm or multi- phase dcm operation modes. 2. after pgood goes high, vid pin recieves a high or low input signal. once the dcm mode is activated, the up1666q automatically reduces switching frequency at light load to maintain high efficiency. as the load current decreases, the rectifying mosfet is turned off when zero inductor current is detected, and the converter runs in discontinuous conduction mode. up1666qs power saving feature is a non-latch-off function, the operation mode can be changed anytime after controller por. table 2. recommended v psi setting in four operation modes edom noitarep ov dednem mocer isp mccesahp-llu fv 8.1 mcdesahp-llu fv 2.1 mccesahp-elgni sv 6.0 mcdesahp-elgni sd ng application of output voltage above 2v the up1666q supports the application of output voltage above 2v through a voltage divider at fb pin. to support this application, connect a 30k ? resistor between lgate1 and gnd. to ensure lgate1 functional setting to work normally, the total capacitance from lgate1 to gnd must not exceed 12nf (including c iss capacitance of low side mosfet). it is recommended to set v refin = v ref or provide a fixed reference voltage for v refin . the output voltage can be programmed as: v out = v refin x (1 + r4/r3) where r1 and r2 are the resistors of the voltage divider on fb pin. the typical application circuit of output above 2v is shown in the section of typical application circuit . over voltage protection (ovp) the ovp is triggered if v fb > 1.5xv refin sustained 10us. when ovp is activated, the up1666 turns on all low-side mosfet and turns off all high-side mosfet. the over voltage protection is a latch-off function and can only be reset by pvcc re-por or en restart. under voltage protection (uvp) the under voltage protection is triggered if v fb < 0.5xv refin sustained 10us. when uvp is activated, the up1666q turns off all high-side and low-side mosfet. the under voltage protection is a latch-off function and can only be reset by pvcc re-por or en restart. over temperature protection (otp) the up1666q monitors the temperature of itself. if the temperature exceeds typical 150 o c, the up1666q is forced into shutdown mode. the over temperature protection is a latch-off function and can only be reset by pvcc re-por or en restart. output ramp up time (t_ramp) the up1666q provides 150us, 450us, 900us, and 1.5 ms output ramp up time selection. the output ramp up time is selected through an external resistor connected between lgate2 to gnd. to ensure lgate2 functional setting to work normally, the total capacitance from lgate2 to gnd must not exceed 12nf (including c iss capacitance of low side mosfet). the output ramp up time is determined and latched off before output soft-start cycle initiates. the following table shows the four output ramp up time and its recommended r lg2 . table 3. recommended r lg2 setting in output ramp up time emitpu pmartuptuo )pmar_t( r dednem mocer 2gl su05 1k 03 ? su05 4k 26 ? su00 9k 021 ? su005 1n epo
up1666q 10 up1666q-ds-f0000, june 2017 www.upi-semi.com functional description power up sequencea built-in soft-start function is used to prevent surge current from power supply input during power on. controller starts the soft-start process right on en (soft-start i). if en asserts in the middle of por initialization, soft-start process is waiting for pvcc_por initialization to complete (soft-start ii). the error amplifier is a three-input device. reference voltage (v refin ) or the internal soft-start voltage (v ss ) whichever is smaller dominates the behavior of the non-inverting inputs of the error amplifier. internal soft-start voltage(v ss ) starts to ramp up linearly with a slew rate determined by r lg2 resistor after the soft-start cycle is initiated. the output voltage will follow the internal soft-start voltage(v ss ) and ramp up linearly. if there is no fault detected at the end of the soft-start, the controller then asserts pgood when the output voltage reaches its target level. the pwmvid signal is ignored before pgood goes high and the output voltage might not follow v refin (which is generated by pwmvid network) during t_vid time. hence, it is recommended to let pwmvid be toggled after t_vid time. the t_vid time can be calculated as : ? ? ? ? ? ? ? ? = boot refin boot refin max refin v ramp t v v vid t , , , _ ) ( _ where, v refin,max is the maximum voltage when pwmvid duty cycle=100%. v refin,boot is the boot voltage generated by pwmvid network. tramp is the output voltage ramp up time determined by r lg2 resistor. the following graphs show the power up sequence of up1666q. pok vout en pvcc por ~ ~ ~ ~ ~ ~ t_init t_ramp t_init_por soft start i ~ ~ vid t_vid ~ ~ pok vout en pvcc por ~ ~ ~ ~ ~ ~ t_init t_ramp t_init_por soft start ii ~ ~ vid t_vid ~ ~ figure 5. soft-start sequence
up1666q 11 up1666q-ds-f0000, june 2017 www.upi-semi.com (note 1) supply input voltage, pvcc ------------------------------------------------------------------------------------------------------------- -0.3v to +6.5v bootx to phasex dc --------------------------------------------------------------------------------------------------------------------------------------- -0.3v to +6v < 100ns ---------------------------------------------------------------------------------------------------------------------------------- -5v to +8v phasex to gnd dc --------------------------------------------------------------------------------------------------------------------------------------- -0.7v to +28v < 100ns ---------------------------------------------------------------------------------------------------------------------------------- -8v to +36v bootx to gnd dc --------------------------------------------------------------------------------------------------------------------------------------- -0.3v to +34v < 100ns ---------------------------------------------------------------------------------------------------------------------------------- -5v to +42v ugatex to phasex dc --------------------------------------------------------------------------------------------------------------------------------------- -0.3v to +6v < 100ns ---------------------------------------------------------------------------------------------------------------------------------- -5v to +7v lgatex to gnd dc --------------------------------------------------------------------------------------------------------------------------------------- -0.3v to +6v < 100ns ---------------------------------------------------------------------------------------------------------------------------------- -5v to +7v other pins --------------------------------------------------------------------------------------------------------------------------------------- -0.3v to +6v storage temperature range -------------------------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature ------------------------------------------------------------------------------------------------------------------------------- -------- 150 o c lead temperature (soldering, 10 sec) -------------------------------------------------------------------------------------------------------------- 260 o c esd rating (note 2) hbm (human body mode) ----------------------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ------------------------------------------------------------------------------------------------------------------------------- - 200v package thermal resistance (note 3) wqfn3x3 - 20l ja ----------------------------------------------------------------------------------------------------------------------- 68 o c/w wqfn3x3 - 20l jc ------------------------------------------------------------------------------------------------------------------------ 6 o c/w power dissipation, p d @ t a = 25 o c wqfn3x3 - 20l -------------------------------------------------------------------------------------------------------------------------------------- 1.47w (note 4) operating junction temperature range --------------------------------------------------------------------------------------------- -40 o c to +125 o c operating ambient temperature range ---------------------------------------------------------------------------------------------- -40 o c to +85 o c input voltage, v in ----------------------------------------------------------------------------------------------------------------------------- - 2.5v to 20v control voltage, v pvcc ----------------------------------------------------------------------------------------------------------------------- 4.5v to 5.5v absolute maximum rating thermal information recommended operation conditions note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 o c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions.
up1666q 12 up1666q-ds-f0000, june 2017 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu tupniylppus tnerructnecseiu qi q ,mcdesahp-1,v8.1=ne gnihctiwson - -0 0 8- -a u tnerrucnwodtuh si ndhs v0=n e- -2- -a u dlohserhtrop ccv pv htrccvp v ccvp .gnisi r9 . 31 . 43 . 4v siseretsyh rop ccv pv syhccvp - -3 . 0- -v ycaruccaegatlovfer vv fer 89. 122 0. 2v tnerrucgnicruosfer vi fer 0 1- -- -a m ne:tupnilortnoc dlohserhtwolcigo lv l_ne - -- -4 . 0v dlohserhthgihcigo lv h_ne 2. 1- -- -v ecnatsisernwod-lluplanretn ir ne - -0 0 2- -k ? emitno htdiwtohsen ot no v ni v,v21= tuo ,v9.0= f ws zhk003= - -0 5 2- -s n emitno mumini mt nim_no - -0 8- -s n emitffo mumini mt nim_ffo - -0 0 3- -s n reifilpmarorre niag cdpoolnep oa o ngisedybdeetnarau g0 70 8- -b d ecnatcudnoc-snar tm g- -0 0 8- -v /au )knis &ecruos(tnerruc mumixa mi pmoc - -0 8- -a u ntrbf tnerruc ntrb fi ntrbf gnihctiwson,v4.1>n e- -- -0 0 5a u tratstfos roptaemitnoitazilaitin it rop_tini_ 5erugifotrefe r- -- -0 5 3s u emitnoitazilaitin it tini_ 5erugifotrefe r- -- -0 5 2s u emittratstfoselbatcele st ss doogpotn e0 5 2- -0 00 2s u isp cigoledom gnivasrewo pv isp mccesahp- 26 . 1- -- - v mcdesahp- 21 - -4 .1 mccesahp- 14 . 0- -8 .0 mcdesahp- 1- -- -2 .0 (pvcc = 5v, t a = 25 o c, unless otherwise specified)
up1666q 13 up1666q-ds-f0000, june 2017 www.upi-semi.com electrical characteristics retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu reffub divm w p levelwoltupnidi vv div_li - -- -6 . 0v levelhgihtupnidi vv div_hi 2. 1- -- -v yaledetats-irt di vt div_irt - -0 0 1- -s n ecnatsiserecruosjdafe rr crs_fb i crs am1 =- -0 2- - ? ecnatsiserknisjdafe rr kns_fb i kns am1 =- -0 2- - ? srevirdetag ecruosetagrepp ur crs_gu i gu am08- =- -12 ? knisetagrepp ur kns_gu i gu am08 =- -5 . 01 ? ecruosetagrewo lr crs_gl i gl am08- =- -12 ? knisetagrewo lr kns_gl i gl am08 =- -4 . 08 .0 ? emitdae dt td - -0 1- -s n edoidykttohcspartstooblanretni egatlovdrawro fv f am5.3=tnerrucsaibdrawro f- -3 3. 0- -v dlohserhtnoitcetedtnerruc orez dlohserhttnerrucore zv cz esahp-dn g- -5 . 0- -v m noitcetorp dlohserhtpc ov co esahp-dn g0 4- -0 0 4v m dlohserhtpv ov pvo v bf v/ nifer - -0 5 1- -% yaled pvo - -0 1- -s u dlohserhtpv uv pvu v bf v/ nifer 0 4- -0 5% yaled pvu - -0 1- -s u dlohserhtpto - -0 5 1- - o c rotacidnidoogrewop rotacidnidoogrewo pv gp i knis am4 =- -- -3 . 0v tnerrucegakaeldoogrewo pi kael_gp v gp v5 =- -- -2 . 0a u
up1666q 14 up1666q-ds-f0000, june 2017 www.upi-semi.com v out 100mv/div ug2 10v/div ug1 10v/div psi 2v/div vout 100mv/div ug2 10v/div ug1 10v/div psi 2v/div vout 100mv/div ug2 10v/div ug1 10v/div psi 2v/div vout 100mv/div ug2 10v/div ug1 10v/div psi 2v/div vout 500mv/div en 2v/div ug1 20v/div pgood 2v/div vout 500mv/div en 2v/div ug1 20v/div pgood 2v/div typical operation characteristics 1 phase dcm to 2 phase dcm time : 20us/div v in = 12v, v out = 0.9v, i out = 2a 1 phase ccm to 2 phase dcm power on from en time : 200us/div v in = 12v, v out = 0.9v, i out = 1a, r lg2 = open power off from en time : 200us/div v in = 12v, v out = 0.9v, i out = 1a, r lg2 = open 1 phase dcm to 2 phase ccm time : 20us/div v in = 12v, v out = 0.9v, i out = 1a 1 phase ccm to 2 phase ccm time : 20us/div v in = 12v, v out = 0.9v, i out = 1a time : 20us/div v in = 12v, v out = 0.9v, i out = 1a
up1666q 15 up1666q-ds-f0000, june 2017 www.upi-semi.com vid 2v/div refadj 1v/div vout 50mv/div vout 500mv/div pgood 2v/div ug1 20v/div il 10a/div fb 500mv/div pgood 2v/div ug1 20v/div lg1 5v/div fb 500mv/div pgood 2v/div ug1 20v/div lg1 5v/div vid 2v/div refin 200mv/div vout 200mv/div vid 2v/div refin 200mv/div vout 200mv/div typical operation characteristics over current protection time : 20us/div v in = 12v, v out = 0.9v, f sw = 300khz, ? v fs = 40mv, low side mosfet = qm3056 (r ds(on) = 4.2m ? ), r1 = 91k ? , r2 = 47k ? pwmvid: 50% pwmvid duty cycle 0% to 100% time : 20us/div v in = 12v, i out = 1a pwmvid duty cycle 100% to 0% time : 20us/div v in = 12v, i out = 1a under voltage protection time : 4us/div v in = 12v, v out = 0.9v, i out = 0a over voltage protection time : 4us/div v in = 12v, v out = 0.9v, i out = 0a time : 1us/div v in = 12v, v out = 0.9v, i out = 0a
up1666q 16 up1666q-ds-f0000, june 2017 www.upi-semi.com 0 10 20 30 40 50 60 70 80 90 100 0 1 02 03 04 05 0 vin = 12v vin = 6v vin = 20v 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 vin = 12v vin = 6v vin = 20v vout 100mv/div ug2 10v/div ug1 10v/div iout 36a/div typical operation characteristics 1 phase dcm efficiency load (a) v cc = 5v, 1 phase dcm operation efficiency (%) 2 phase ccm efficiency load (v) v cc = 5v, 2 phase ccm operation efficiency (%) load transient time : 20us/div v in = 12v, v out = 0.9v, i out = 1-50a, f sw = 300khz, 2 phase ccm, l = 0.22uh, c = 2848uf
up1666q 17 up1666q-ds-f0000, june 2017 www.upi-semi.com package information note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. wqfn3x3 - 20l 2.90 - 3.10 pin 1 mark bottom view - exposed pad 1.40-1.80 0.15 - 0.25 1.40 - 1.80 0.30 - 0.50 2.90 - 3.10 0.00 - 0.05 0.70 - 0.80 0.20 ref
up1666q 18 up1666q-ds-f0000, june 2017 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. however, no responsibility is assumed by upi or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. no upi components are designed, intended or authorized for use in military, aerospace, automotive applications nor in systems for surgical implantation or life-sustaining. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2015, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064

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